Differential inverter circuit

ABSTRACT

An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.

This application is a continuation of U.S. patent application Ser. No.10/501,427, filed on Dec. 12, 2002, and claims the benefit thereof. Thecontents of U.S. patent application No. 10/501,427 is incorporatedherein by reference.

The invention relates to an improved differential inverter as describedin the preamble of Claim 1.

Inverters are very useful electronic devices embedded in both analog anddigital circuits. In CMOS technology the inverters architecture is verysimple as shown in FIG. 7. The inverter in FIG. 7 comprises a transistorpair, said transistor pair comprising a p-type MOS transistor (T1)coupled to a n-type MOS transistor (T2). The transistors are drain todrain coupled, their control terminals G1 and G2 being connected to eachother. In a digital application a binary input signal (Vin) is appliedto the transistors control terminals (G1, G2). At an output of theinverter is obtained an output signal (OUT) having one of the possiblebinary values, i.e. either logical 1 or logical 0, said output signal(OUT) being substantially 180 degree phase-shifted versus the inputsignal. In linear applications a feedback resistor (R) is connectedbetween the transistors drains and the transistors grids. In this way astable operating point for the transistor pair is obtained. For thisapplication an important parameter is the transconductance gm of thetransistor pair. Mathematically the transconductance could be expressedas in relation (1).gm=β(V _(GS) −V _(TH))  (1)In relation (1) β is a parameter depending on geometrical properties ofthe transistors i.e. it's width (W) and it's length (L). V_(GS) is avoltage between the grid and the source of the transistor. V_(TH) is athreshold voltage i.e. the voltage required for the transistor to turnon and to conduct a drain current. V_(TH) also depends on thetechnology. From relation (1) results that the transconductance gm couldbe controlled by controlling one or a combination of the parameters β,V_(GS), V_(TH). In applications where a supply voltage for thetransistor pair is relatively low e.g. 0.5 V it is necessary to obtainan as large as possible gm in applications like buffering andoscillation generation.

In U.S. Pat. No. 4,387,349 is considered an inverter used in a crystaloscillator for generating an oscillation. The crystal oscillatordisclosed in this patent is realized using a CMOS transistor paircomprising a p-type transistor connected to a n-type transistor. Thegrids of the transistors are coupled via a capacitor. Each of the gridsis further coupled to a reference voltage generator for biasing thetransistor pair in class B. In oscillators this could be a suitablesolution for biasing but when linear applications are considered thebuffer must be biased in class A for providing a maximum linearity. Asuitable inverter suitable for both linear applications and oscillationgeneration could be therefore realized in a device having differentreference voltages, reference voltages depending on the type of theapplication i.e. linear or oscillation generation. This solutionincreases the complexity and cost of the circuit. Furthermore indifferential applications where two transistor pairs are used, it isdesirable that both transistor pairs have substantially equalcharacteristics as e.g. gm and DC operating point. This istechnologically impossible to be obtained with a fix bias and couldresult in a differential stage that does not work properly. That is whyit is desirable to have biasing for transistor pairs used indifferential applications for both linear applications and oscillationsgeneration.

It is therefore an object of the present invention to provide animproved CMOS inverter suitable for differential applications.

In accordance with the invention this is achieved in a device asdescribed in the preamble of claim 1 being characterized in that itfurther comprises a controlled bias generator generating the secondvector of input signals in response to a bias control signal which isgenerated at an output of a voltage divider coupled to the differentialoutput of the differential inverter said bias control signal beingindicative for a DC voltage of the of the differential output.

A differential inverter has two output terminals for generating thefirst output signal and the second output signal that are substantiallyin anti-phase i.e. phase shifted with 180 degrees to each other. Tworesistor means equal to each other e.g. in the simplest way simpleresistors are connected in series to each other between the outputterminals. Because the first and the second output signals are inanti-phase an AC voltage measured in the connection point of the tworesistor means would be substantially zero volt. In the same time, a DCvoltage measured in the same point would be substantially an average ofthe DC voltages of the outputs of the inverter. ADC voltage differencebetween the two outputs is sensed and a bias control signal isgenerated. The bias control signal is inputted to a controlled biasgenerator, said controlled bias generator generating the second pair ofinput signals comprising a first control signal and a second controlsignal. The first control signal and the second control signals are DCvoltage signals controlling the differential inverter in such a way thata DC difference between the first output signal and the second outputsignal is as small as possible, ideally zero.

In an embodiment of the invention the differential inverter comprises afirst transistor pair and a second transistor pair each of thetransistor pairs comprising a n-type MOS transistor coupled to a p-typeMOS transistor via a drain to drain connection, the n-type transistorhaving a first control terminal for receiving a component of the secondvector of input signals via a third resistor means and the p-typetransistor having a second control terminal for receiving a component ofthe second vector of input signals via a fourth resistor means.

In another embodiment of the invention the control bias generatorcomprises a first CMOS inverter coupled to a second CMOS inverter and toa third CMOS inverter, the first CMOS inverter receiving the biascontrol signal and generating a variable control signal proportional tothe bias control signal to be inputted in the second CMOS inverter andin the third CMOS inverter, the second CMOS inverter and the third CMOSinverter generating the second vector of input signals in response tothe variable control signal. When the bias control signal issubstantially half of the supply voltage the first control signal is avoltage higher than half of a supply voltage and the second controlsignal is lower than half of the supply voltage. The third and thesecond control signals determines the V_(GS) voltages of the transistorpairs in the differential inverter that further determines the gmparameter of the transistor pairs as results from relation (1).

In an embodiment of the invention any of the CMOS inverters included inthe controlled bias generator comprises a pair of p-type MOS transistorcoupled to n-type MOS transistor said transistors having differentgeometrical properties. If a MOS transistor pair is realized withmatched transistors the output DC voltage is, ideally, half of thesupply voltage. A drain current of a MOS transistor depends, in a firstapproximation, on the geometrical properties of the transistor as inequation (2). $\begin{matrix}{I_{D} = {k\frac{W}{L}\left( {V_{GS} - V_{TH}} \right)^{2}}} & (2)\end{matrix}$

In equation (2) I_(D) is the drain current, k depends on the technologyused, W is a width of the transistor and L is a length of thetransistor, the other symbols being as in equation (1). A geometricalparameter that could better define the geometrical properties of the MOStransistors is their area, i.e. A=W*L. In a specific technology one ofthe area parameters is maintained constant for all the transistors e.g.L, while the other is modified e.g. W. Using this procedure transistorscould be obtained having different electrical characteristics as it isindicated in relation (2).

In another embodiment of the invention it is presented a differentialoscillator comprising an improved differential inverter, saiddifferential oscillator having a LC tank circuit coupled between thedifferential output terminals of the improved differential inverter, thedifferential output terminal being cross-coupled to the differentialinput.

In oscillation applications it is desirable to use as efficient aspossible the power supply source especially when relatively low voltagee.g. 0.5 V battery operating circuits are considered. That is why inthese applications the classical oscillator circuits cannot be used.Because of the technological imperfections the DC output of thetransistor pairs is not half of the supply voltage and the transistorpair does not provide a high gm and either the oscillator does not startit's oscillation or the oscillation is not symmetrical. The oscillatorof the present invention has a bias that is continuously adapted to thevariations of the DC operating point of the transistor pairs.

The above and other features and advantages of the invention will beapparent from the following description of the exemplary embodiments ofthe invention with reference to the accompanying drawings, in which:

FIG. 1 depicts a block diagram of an improved differential inverteraccording to the present invention,

FIG. 2 depicts a detailed diagram of a transistor pair included in thedifferential inverter according to the present invention,

FIG. 3 depicts an embodiment of the controlled bias generator accordingto the present invention,

FIG. 4 depicts an embodiment of an inverter included in the controlledbias generator according to the invention,

FIG. 5 depicts a block diagram of an oscillator using the improveddifferential inverter according to the invention,

FIG. 6 depicts a detailed diagram of the oscillator according to theinvention

FIG. 7 depicts a CMOS inverter as known in the art,

FIG. 1 depicts a block diagram of an improved differential inverteraccording to the present invention. The improved differential inverter100 comprises a differential inverter 30 having a differential input forreceiving a first vector of signals comprising a first input signal DIN1and a second input signal DIN2. The improved differential inverter 100further comprises a differential control input for receiving a secondvector of input signals said vector comprising a first a first controlsignal DC1 and a second control signal DC2. The improved differentialinverter has a differential output for transmitting a third vector ofdifferential signals said vector comprising a first output signal OUT1and a second output signal OUT2.

The improved differential inverter 100 further comprises a controlledbias generator 10 generating the second vector of input signalscomprising a first control signal DC1 and a second control signal DC2.Said second vector of signals is generated in response to a bias controlsignal Cin. The bias control signal is obtained in a coupling point P ofa first resistor means Ros1 to a second resistor means Ros2substantially equal to the first resistor means Ros1. An end of thefirst resistor means Ros1 and an end of the second resistor means Ros2are coupled to the differential output. If we note the DC voltage of thesignal OUT1 as V₁ and the DC voltage of the signal OUT2 as V₂ the DCvoltage measured in the point P is (V₁+V₂)/2. It should be pointed outhere that because an AC component of V₁ is substantially in anti-phasewith an AC component of V₂ the AC component in the voltage measured inpoint P is substantially zero. Ideally V1 equals the voltage V2 and V₂equals half of the supply voltage of the transistor pair. In thissituation the DC voltage measured in point P is half of the supplyvoltage. In a real circuit there is a difference between V₁ and V₂ theDC voltage measured in the point P being either above or below half ofthe supply voltage. This determines the controlled bias generator 10 toprovide a second vector of input signals for controlling the bias of thedifferential inverter in such a way that the transconductance of thedifferential inverter 10 is as high as possible.

FIG. 2 depicts a detailed diagram of a transistor pair included in thedifferential inverter according to the present invention. Thedifferential inverter 10 comprises a first transistor pair and a secondtransistor pair. Each of the transistor pairs comprises a n-type MOStransistor T2 coupled to a p-type MOS transistor T1 via a drain to drainconnection. The n-type transistor T2 has a first control terminal G2 forreceiving the second control signal DC2 via a third resistor means R1.The p-type transistor T1 has a second control terminal G1 for receivingthe first control signal DC1 of the second vector of input signals via afourth resistor means R1 The third resistor means R1 and the fourthresistor means R1 couple the gates of the transistors to the firstcontrol signal DC1 and to the second control signal DC2 respectively.The first control signal is lower than half of the supply voltage Vddand the second control signal DC2 is higher than half of the supplyvoltage Vdd. Capacitors C1 are used to de-couple the AC currentcomponents from DC current components and must have a much lowerimpedance value than the parasitic input capacitance of the transistors.

FIG. 3 depicts an embodiment of the controlled bias generator 10according to the present invention. The control bias generator 10comprises a first CMOS inverter 11 coupled to a second CMOS inverter 12and to a third CMOS inverter 13. The first CMOS inverter 11 receives thebias control signal Cin and generates a variable control signal VR to beinputted in the second CMOS inverter 12 and in the third CMOS inverter13. The second CMOS inverter 12 and the third CMOS inverter generate thesecond vector of input signals DC1, DC2 in response to the variablecontrol signal VR.

FIG. 4 depicts an embodiment of an inverter included in the controlledbias generator 10 according to the invention. Any of the invertersincluded in the controlled bias generator comprises a pair of CMOStransistors T₁, and T₂ connected drain to drain. Their controlledterminals i.e. gate terminals are also connected to each other. Thetransistors are characterized in that they have different geometricalproperties i.e. they have different areas A1 and A2, respectively.Normally the length L of the two transistors is equal to each otherwhile their width W is different. In this way the DC operating pointe.g. their drain currents depend on the geometrical properties of thetransistors as results from relation (2). In the situation when thedrain currents are equal to each other i.e. the transistors have equalareas the DC voltage measured at their drain terminals is half of thesupply voltage, otherwise the DC voltage depends on a ratio of the areasof the transistors.

FIG. 5 depicts a block diagram of an oscillator 400 using the improveddifferential inverter 100 according to the invention. The differentialoscillator 400 comprises an improved differential inverter 100, saiddifferential oscillator 400 having a LC tank circuit 401 coupled betweenthe differential output terminals of the improved differential inverter100, the differential output terminal being cross-coupled to thedifferential input. With this circuit a periodical waveform isgenerated. The LC tank circuit 401 determines the oscillation frequencyof the oscillator 400. In relatively low voltage supply applicationse.g. 0.5 V it is very important that the oscillator provides as much aspossible energy at it's output in order to use the supply source asefficient as possible. The efficiency is substantially maximal when a DCvoltage at any of the oscillator outputs is half of the supply voltagewhen sinusoidal oscillation is considered. Sinusoidal oscillation isnecessary especially in applications as e.g. mixers in transceivers. Inapplications where the physical conditions are not so tight e.g. inquartz based oscillators the differential control input terminals of thedifferential inverter could be connected to fixed voltage terminals e.g.the reference terminal and the power supply terminal as in U.S. Pat. No.4,095,195. This solution is not suitable for a LC oscillator working atrelatively low supply voltage because if technologically the transistorsincluded in a transistor pair are not substantially identical to eachother the oscillation could not start. In the present application, evenif the transistors are not technologically identical to each other thecontrolled bias generator provides the proper DC bias signals for thetransistors in response to the control Cin signal and the oscillationstarts easily.

FIG. 6 depicts a detailed diagram of the oscillator 400 according to theinvention. In FIG. 6 the building blocks previously described areidentified in dotted lines. The differential inverter 30 is realizedwith a first pair of transistors M1, M2 and a second pair of transistorsM1′ and M2′. The third resistor means R1 couples the gates of thetransistors either to the first control signal DC1 or to the secondcontrol signal DC2. The first control signal is lower than half of thesupply voltage Vdd and the second control signal DC2 is higher than halfof the supply voltage Vdd . Capacitors C1 are used to de-couple the ACcurrent components from DC current components and must have a much lowervalue than the parasitic input capacitance of the transistors. Theinverters 11, 12 and 13 are realized with the transistor pairs (T1′,T2′), (T1″, T2″) and (Ti″′, T2″′) respectively. Each of the transistorpairs included in the inverters comprises transistors having differentarea.

It is remarked that the scope of protection of the invention is notrestricted to the embodiments described herein. Neither is the scope ofprotection of the invention restricted by the reference numerals in theclaims. The word ‘comprising’ does not exclude other parts than thosementioned in the claims. The word ‘a(n)’ preceding an element does notexclude a plurality of those elements. Means forming part of theinvention may both be implemented in the form of dedicated hardware orin the form of a programmed purpose processor. The invention resides ineach new feature or combination of features. The term ‘grid’ and ‘gate’refer to the control input of a MOS transistor.

1. An improved differential inverter (100) comprising a differentialinverter (30) having a differential input for receiving a first vectorof signals comprising a first input signal (DIN1) and a second inputsignal (DIN2) a differential control input for receiving a second vectorof input signals comprising a first a first control signal (DC1) and asecond control signal (DC2), a differential output for transmitting athird vector of differential signals comprising a first output signal(OUT1) and a second output signal (OUT2) said improved differentialinverter (100) being characterized in that it further comprises acontrolled bias generator (10) generating the second vector of inputsignals in response to a bias control signal (Cin) which is generated atan output of a voltage divider coupled to the differential output of thedifferential inverter (30) said bias control signal being indicative ofa DC voltage of the of the differential output, wherein the controlledbias generator comprises a first inverter having an output that is thefirst control signal and a second inverter having an output that is thesecond control signal.
 2. An improved differential inverter (100) asclaimed in claim 1 wherein the bias control signal (Cin) is generated ina coupling point (P) of a first resistor means (Ros1) to a secondresistor means (Ros2) substantially equal to the first resistor means(Ros1), an end of the first resistor means (Ros1) and an end of thesecond resistor means being coupled to the differential output.
 3. Animproved differential inverter (100) as claimed in claim 1 wherein thedifferential inverter (30) comprises a first transistor pair and asecond transistor pair each of the transistor pairs comprising a n-typeMOS transistor (T2) coupled to a p-type MOS transistor (T1) via a drainto drain connection, the n-type transistor (T2) having a first controlterminal (G2) for receiving the second control signal (DC2) via a thirdresistor means (R3), the p-type transistor (T1) having a second controlterminal (G1) for receiving the first control signal (DC1) via a fourthresistor means (R4).
 4. An improved differential inverter (100) asclaimed in claim 1 wherein the control bias generator (10) comprises afirst CMOS inverter (11) coupled to a second CMOS inverter (12) and to athird CMOS inverter (13), the first CMOS inverter (11) receiving thebias control signal (Cin) and generating a variable control signal (VR)that is inputted to the second CMOS inverter (12) and to the third CMOSinverter (13), the second CMOS inverter (12) and the third CMOS invertergenerating the second vector of input signals (DC1, DC2) in response tothe variable control signal (VR).
 5. An improved differential inverter(100) as claimed in claim 4 wherein any of the CMOS inverters includedin the controlled bias generator (10) comprises a pair of a p-type MOStransistor (T1′) and a n-type MOS transistor (T2′) said transistorsbeing mutually coupled and having different geometrical properties A1′and A2′, respectively.
 6. A differential oscillator (400) comprising animproved differential inverter (100) as claimed in claim 1, saiddifferential oscillator having a LC tank circuit (401) coupled betweenthe terminals of the differential output of the improved differentialinverter (100), the terminals of the differential output beingcross-coupled to the differential input.
 7. A differential invertercomprising: a differential input operative to receive a first vector ofsignals comprising a first input signal and a second input signal; adifferential control input operative to receive a second vector of inputsignals comprising a first a first control signal and a second controlsignal; a differential output adapted to transmit a third vector ofdifferential signals comprising a first output signal and a secondoutput signal; and a controlled bias generator operative to generate thesecond vector of input signals in response to a bias control signal,which is generated at an output of a voltage divider coupled to thedifferential output of the differential inverter, wherein the biascontrol signal is indicative of a DC voltage of the of the differentialoutput, wherein the controlled bias generator comprises a first inverterhaving an output that is the first control signal and a second inverterhaving an output that is the second control signal.